A conventional analog circuit 100, as shown in FIG. 21 (denoted by first conventional analog PLL circuit in the following) is composed of a Phase Frequency Detector (denoted by PFD in the following), a low-pass filter 101 of capacitor Cm, a Voltage Controlled Oscillator 102 (denoted by VCO in the following) and a Divider 5 (denoted by DIV in the following). The VCO 102 in the first conventional PLL circuit 100 is an oscillation circuit which is configured to change an oscillation frequency by controlling voltage and output an intended oscillation frequency from an output unit 6.
Here, a reference clock frequency inputted from outside via an input unit 2 and an oscillation frequency obtained by dividing the output from VCO 102 with DIV 5 are inputted into PFD 3. PFD 3 compares phases of these two frequencies. The first conventional analog PLL circuit 100 stores electric charge in the capacitor Cm of the low-pass filter 101 according to the phase difference outputted from PFD 3. And the first conventional analog PLL circuit 100 controls voltage of VCO 102 based on the charge (voltage) stored in the capacitor Cm of the low-pass filter 101.
Then, the oscillation frequency outputted from VCO 102 via DIV 5 is locked in a target frequency using feedback loop. As described above, in the first conventional analog PLL circuit 100, the output pulse signal from PFD 3 is converted into analog control voltage low-pass filtered by the low-pass filter 101 of capacitor Cm. And using the analog control voltage, the first conventional analog PLL circuit 100 is configured to control the frequency of VCO 102.
As another analog PLL circuit, an analog PLL circuit 110 (denoted by second conventional analog PLL circuit in the following) as shown in FIG. 22, where corresponding units are indicated by the same reference signs with those of FIG. 21, is also known (for example, refer to Non Patent Literature 1 and 2). This second conventional analog PLL 110 includes a circuit 111 with PFD and a Charge Pump (denoted by PFD/CP in the following). In the second conventional analog PLL circuit 110, as in the first conventional analog PLL circuit 100 described above, the output pulse signal from PFD/CP 111 is converted into analog control voltage low-pass filtered by the low-pass filter 113 of capacitor Cm. And using the analog control voltage, the second conventional analog PLL circuit 110 is configured to control the frequency of VCO 102.
In addition to the first conventional analog PLL circuit 100 and the second conventional analog PLL circuit 110, another example of conventional technique is a digital PLL circuit 120 (denoted by conventional digital PLL circuit in the following), as shown in FIG. 23 is also known. In the conventional digital PLL circuit 120, a Time to Digital Converter 121 (denoted by TDC in the following) converts the pulse width of an output pulse signal into digital bits. The digital bit then goes through a Digital Filter 122 (denoted by DF in the following), which can output a digital bit to control the frequency of a Digital Controlled Oscillator 123 (denoted by DCO in the following) (for example, refer to Non Patent Literature 3 and 4).